Simulated Annealing Approach onto VLSI Circuit Partitioning

Abstract

Decompositions of inter-connected components, to achieve modular independence, poses the major problem in VLSI circuit partitioning. This problem is intractable in nature, Solutions of these problems in computational science is possible through appropriate heuristics. Reduction of the cost that occurs due to interconnectivity between several VLSI components is referred to in this paper. Modification of results derived by classical iterative procedures with probabilistic methods is attempted. Verification has been done on ISCAS-85 benchmark circuits. The proposed design tool shows remarkable improvement results in comparison to the traditional one when applied to the standard benchmark circuits like ISCAS-85.